\doxysection{FMC\+\_\+\+Bank1\+E\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_m_c___bank1_e___type_def}{}\label{struct_f_m_c___bank1_e___type_def}\index{FMC\_Bank1E\_TypeDef@{FMC\_Bank1E\_TypeDef}}


Flexible Memory Controller Bank1E.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank1_e___type_def_abd27ba74f0c9b180f713e7fad065a8d9}{BWTR}} \mbox{[}7\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Flexible Memory Controller Bank1E. 

\label{doc-variable-members}
\Hypertarget{struct_f_m_c___bank1_e___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_m_c___bank1_e___type_def_abd27ba74f0c9b180f713e7fad065a8d9}\index{FMC\_Bank1E\_TypeDef@{FMC\_Bank1E\_TypeDef}!BWTR@{BWTR}}
\index{BWTR@{BWTR}!FMC\_Bank1E\_TypeDef@{FMC\_Bank1E\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BWTR}{BWTR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank1_e___type_def_abd27ba74f0c9b180f713e7fad065a8d9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank1\+E\+\_\+\+Type\+Def\+::\+BWTR\mbox{[}7\mbox{]}}

NOR/\+PSRAM write timing registers, Address offset\+: 0x104-\/0x11C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
